1. Field of the Invention
The present invention relates generally to copper interconnects. More particularly, the present invention relates to a via-first dual damascene process capable of avoiding bridging defects.
2. Description of the Prior Art
Damascene processes incorporated with copper interconnect technique are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. The continuous miniaturization of copper chip wiring and consequently shrinkage of line width and via size/space poses significant challenges.
In a via-first approach, the vias are defined first in the inter-layer dielectric, followed by patterning the trenches. The sequence of forming the damascene recesses in the via-first approach begins by exposing the via patterns with the first mask. After etching the vias completely through the entire dielectric stack (except not through the barrier layer at the bottom of the dielectric stack) and stripping the resist, a second mask is used to pattern the trenches. The trenches are then created by etching the dielectric down to the embedded etch-stop layer.
Typically, the barrier layer at the bottom of the vias is protected from further etching during the trench-etch by a resist layer that floods the vias. After the resist is stripped and the etch-stop layer at the bottom of the via is removed by dry-etching, the metal that fills both the vias and the trenches can be deposited. After deposition, it is polished back to create the dual-damascene structure.
FIGS. 1–5 are schematic, cross-sectional diagrams showing several typical intermediate phases of a semiconductor wafer during the via-first dual damascene process according to the prior art method. As shown in FIG. 1, conductive structures 111 and 112 such as damascened copper wirings are provided in a device layer 101 of a semiconductor substrate 100. A capping layer 115 such as silicon nitride is deposited to cover the exposed conductive structures 111 and 112, and the device layer 101. A dielectric stack 120 is then deposited on the capping layer 115. The dielectric stack 120 is composed of a first dielectric layer 121, a second dielectric layer 123, and an etch stop layer 122 interposed between the first dielectric layer 121 and the second dielectric layer 123. A silicon oxy-nitride layer 130 is then deposited on the first dielectric layer 121.
A first photoresist layer 140 having via openings 141 and 142 is formed on the silicon oxy-nitride layer 130, assuming that the via opening 141 is an isolated via pattern, i.e. there is no other via opening located in the proximity of the via opening 141, and the via opening 142 is a dense via pattern. Using the first photoresist layer 140 as a etching mask, an etching process is performed to etch away, in the order of, the silicon oxy-nitride layer 130, the dielectric stack 120, to the capping layer 115, through the via openings 141 and 142, thereby forming via holes 151 and 152a/b. 
As shown in FIG. 2, after stripping the first photoresist layer 140 off the silicon oxy-nitride layer 130, a gap-filling polymer (GFP) layer 200 is coated on the semiconductor substrate 100 and fills the via holes 151 and 152a/b. The GFP layer 200 is typically composed of resist materials known in the art. Coating of the GFP layer 200 is known in the art and an additional post-baking step may be carried out if desired.
As shown in FIG. 3, the GFP layer 200 is then etched back to a predetermined depth so as to form plug 201 in the isolated via hole 151 and plugs 202a/202b in the dense via holes 152. The top surface of the plugs 201 and 202a/b is lower than the top surface of the silicon oxy-nitride layer 130, forming recesses 301, 302a and 302b. As shown in FIG. 4, a second photoresist layer 400 is coated on the semiconductor substrate 100 and fills the recesses 301 and recesses 302a/b using methods known in the art such as spin coating.
As shown in FIG. 5, following the coating of the second photoresist layer 400, a lithographic process is carried out. The exposed second photoresist layer 400 is developed using a proper developer. Trench 411 is formed above the recess 301, trench 412a is formed directly above the recess 302a, and trench 412b is formed directly above the recess 302b. 
Please refer to FIG. 6 and briefly back to FIG. 5, wherein FIG. 6 is a plan view of the via holes and trench patterns of the second photoresist layer 400 of FIG. 5, and FIG. 5 is a cross-sectional view taken along line I—I of FIG. 6. As shown in FIGS. 5 and 6, the line width L of the trench 412a is equal to the diameter of the underlying via hole 152a. Likewise, the line width of the trench 412b is equal to the diameter of the underlying via hole 152b. The line width of the trench pattern 411 is larger than the diameter of the underlying via hole 151.
One drawback of the above-described prior art method is that when etching trench lines into the dielectric stack 120 in the following trench forming step, the exposed first dielectric layer 121 of the dielectric stack 120 in the recesses 301, 302a and 302b are also laterally etched. Since the via 152a and via 152b are very close to each other, such lateral etch of the exposed first dielectric layer 121 between the dense via 152a and 152b usually causes bridging defect after copper CMP.